With the recent increase in the integration density of a DRAM (dynamic random access memory) device, many methods have been proposed to increase capacitance within a limited cell area. These methods generally entail thinning the dielectric film, increasing the effective area of the capacitor plates, using a material having a higher dielectric constant, or combining two or more of the foregoing procedures. Thinning of the dielectric film below 100 .ANG. leads to inferior reliability in a large-capacitance memory device owing to Fowler-Nordheim current. Simply increasing the area of the capacitor plates within a limited cell area requires stacking up the capacitors in multiple levels, which increases the cost per unit and reduces production yield. So a material of a high dielectric constant such as SrTiO.sub.3 (hereunder, STO) or (Ba, Sr)TiO.sub.3 (hereunder, BSTO) as the dielectric film is customarily used to increase the capacitance.
However, in case where capacitors utilizing the high-dielectric-constant material are arranged side-by-side in close proximity, stray capacitance occurs between adjoining storage electrodes. The stray capacitance is a particular problem where a layer of high-dielectric-constant material extends continuously from between the plates or electrodes in one of the side-by-side capacitors to between plates or electrodes in the other of the side-by-side capacitors. Patterning of the layer of high-dielectric-constant material so it is discontinuous between the side-by-side capacitors is a possible solution to this problem, but presents some processing problems, certain ones of which reduce the effective area of the capacitor plates somewhat. The stray capacitance between side-by-side capacitors, particularly serious when the dielectric layer is formed with the high-dielectric-constant material, can cause faulty operation of the device they are incorporated in. When it is desired to change the charge stored on just one of the capacitors, the charge stored on the other of the capacitors will undesirably exhibit some change also, because of coupling between the side-by-side capacitors through the stray capacitance.
FIGS. 1A-1C are sections illustrating step by step a conventional method for fabricating a capacitor in a semiconductor device.
Referring to FIG. 1A, after an electrical insulation layer 12 is formed on a semiconductor substrate 10, a contact hole for exposing a contact area in the surface of the substrate 10 is formed. A conductive plug 14 is formed by filling the contact hole with conductive material. Then, a conductive layer 16 is formed by depositing the conductive material on the resultant and a mask layer 18 is formed by patterning after depositing oxide.
Referring to FIG. 1B, storage electrodes 17 are formed by selectively etching the conductive layer 16 using the mask layer 18 of FIG. 1A as an etching mask.
Referring to FIG. 1C, a dielectric film 20 and a capacitor plate electrode 22 are successively formed by depositing an insulator such as BSTO and conductive material on the structure resulting from forming the storage electrodes 17. Reference mark S indicates portions of the dielectric film 20 across which stray capacitance occurs between adjacent ones of the storage electrodes 17. The capacitor plate electrode 22 covers the sides of the storage electrode as well as its top. In large DRAMs (256 Mb and larger) the capacitance between the plate electrode and the side surfaces of a storage electrode is a significant portion of the total capacitance between the plate electrode and the storage electrode. For example in a 1 Gb DRAM in which the height of the storage electrodes is about 1000 .ANG., the capacitance between the plate electrode and the side surfaces of a storage electrode has typically been about half the capacitance between the plate electrode and the top surface of the storage electrode. That is, the capacitance between the plate electrode and the side surfaces of a storage electrode is about 35% of the total capacitance between the plate electrode and the storage electrode.
The stray capacitance between adjacent ones of the storage electrodes 17 is eliminated in the invention by changing the shape of the capacitor plate electrode 22 so that it provides an electrostatic shield between each pair of adjacent ones of the storage electrodes 17. This is facilitated by forming a respective trench in the electrical insulation layer 12 surrounding each of the storage electrodes 17. The dielectric film 20 dips down into this trench, leaving a portion of this trench to be filled by the capacitor plate electrode 22. The capacitor plate electrode 22 wraps further around each storage electrode 17. The dielectric film 20 is typically about 500 .ANG. thick. So, in modified capacitor structures embodying the invention the capacitance between the plate electrode and the side surfaces of a storage electrode can be more than the capacitance between the plate electrode and the top surface of the storage electrode. That is, the capacitance between the plate electrode and the side surfaces of a storage electrode is typically about 65% of the total capacitance between the plate electrode and the storage electrode. This increased capacitance, owing to greater effective plate area in modified capacitor structures embodying the invention, is a significant additional advantage of these modified capacitor structures.